CS1013 ADVANCED COMPUTER ARCHITECTURESYLLABUS B.E. COMPUTER SCIENCE AND ENGINEERING ANNA UNIVERSITY CHENNAI– REGULATIONS – 2004

ANNA UNIVERSITY CHENNAI: CHENNAI – 600 025
B.E DEGREE PROGRAMME COMPUTER SCIENCE AND ENGINEERING
(Offered in Colleges affiliated to Anna University)
CURRICULUM AND SYLLABUS – REGULATIONS – 2004
B.E. COMPUTER SCIENCE AND ENGINEERING
LIST OF ELECTIVES

CS1013 ADVANCED COMPUTER ARCHITECTURE

AIM
To do an advanced study of the Instruction Set Architecture, Instruction Level Parallelism with hardware and software approaches, Memory and I/O systems and different multiprocessor architectures with an analysis of their performance.

OBJECTIVES
• To study the ISA design, instruction pipelining and performance related issues.
• To do a detailed study of ILP with dynamic approaches.
• To do a detailed study of ILP with software approaches.
• To study the different multiprocessor architectures and related issues.
• To study the Memory and I/O systems and their performance issues.

UNIT I INTRODUCTION 9
Fundamentals of Computer Design – Measuring and reporting performance – Quantitative principles of computer design. Instruction set principles – Classifying ISA – Design issues. Pipelining – Basic concepts – Hazards – Implementation – Multicycle operations.

UNIT II INSTRUCTION LEVEL PARALLELISM WITH DYNAMIC APPROACHES 9
Concepts – Dynamic Scheduling – Dynamic hardware prediction – Multiple issue – Hardware based speculation – Limitations of ILP.

UNIT III INSTRUCTION LEVEL PARALLELISM WITH SOFTWARE APPROACHES 9
Compiler techniques for exposing ILP – Static branch prediction – VLIW – Advanced compiler support – Hardware support for exposing more parallelism – Hardware versus software speculation mechanisms.

UNIT IV MEMORY AND I/O 9
Cache performance – Reducing cache miss penalty and miss rate – Reducing hit time – Main memory and performance – Memory technology. Types of storage devices – Buses – RAID – Reliability, availability and dependability – I/O performance measures – Designing an I/O system.

UNIT V MULTIPROCSSORS AND THREAD LEVEL PARALLELISM 9
Symmetric and distributed shared memory architectures – Performance issues – Synchronization – Models of memory consistency – Multithreading.

TOTAL : 45
TEXT BOOK
1. John L. Hennessey and David A. Patterson, ”Computer Architecture: A Quantitative Approach”, Morgan Kaufmann, 2003, Third Edition.
REFERENCES
1. D.Sima, T.Fountain and P.Kacsuk, ”Advanced Computer Architectures: A Design Space Approach”, Addison Wesley, 2000.
2. Kai Hwang and Zhi.Wei Xu, “Scalable Parallel Computing”, Tata McGraw-Hill, New Delhi, 2003.